The inventive concept relates to semiconductor memory devices, and more particularly, to latency circuits incorporated within semiconductor memory devices, wherein the latency circuits are capable of generating a latency signal using a 1-division or 2-division method according to a column address strobe (CAS) latency.
Different types of semiconductor memory devices are used to implement various memories within a computer system or consumer electronic device (hereafter, generically referred to as “the system”). The speed at which data may be input to and output from a semiconductor memory device is a very important factor in determining the overall operating characteristics of the system. In order to increase overall operating speed of the system, synchronous dynamic random access memory (SDRAM) is commonly used. The SDRAM includes internal circuits that are synchronously controlled in relation to a clock signal generated within the system.
In order to increase its operating speed (or frequency), the SDRAM uses the so-called CAS latency function. CAS latency indicates the number of clock cycles between the time at which a read command is applied to the SDRAM device and the time at which corresponding data is output. Thus, the SDRAM reads data in response to a received read command, and then outputs the “read data” following the number of clock cycles defined by the CAS latency. For example, when a CAS latency is defined as 8 cycles, read data is output synchronously with an output clock eight (8) clock cycles following receipt of the read command.
A latency circuit is used to generate a latency signal. The latency signal is essentially an output control signal that determines when read data may be output from a SDRAM in response to a read command. Thus, the latency circuit may be viewed as a type of data output control (or output enabling) circuit. The data output buffer(s) typically associated with synchronous memory devices such as SDRAMs provide read data in response to the output clock signal during a period in while the latency signal is activated. Accordingly, after a read command is received, the latency circuit provides a latency signal before the predetermined number of clock cycles defined by the CAS latency has elapsed.
The latency signal may be generated as an internal read command signal generated by decoding a read command latched by the output clock signal (or clock signals derived from (i.e., delaying) the output clock signal). Conventionally, the pulse width of the internal read command signal corresponds to one (1) cycle of an external clock, and the output clock signal is generated in response to a delay locked loop (DLL) generated clock signal having the same frequency as the external clock.
When the frequency of the external clock increases, the timing margin between the internal read command signal and the output clock signal decreases. In other words, when the frequency of the external clock increases, the pulse width of the internal read command signal decreases, and the phase of the output clock signal precedes the pulse width of the internal read command signal. Also, the internal read command signal is related to (within the domain of) the external clock, and the output clock signal is related to (within the domain of) the DLL clock. Thus, a timing skew between these two domains may be affected by clock frequency variations, and variations in ambient environmental conditions such as pressure and temperature.
When the margin between the internal read command signal and the output clock signal decreases or the phase of the output clock signal precedes the pulse width of the internal read command signal, the internal read command signal cannot be normally latched, and thus a correct counting of clock cycles relative to the defined CAS latency is not possible. As a result, the internal read command signal is conventionally latched using a 2-divided output clock signal to thereby generate the latency signal. In this manner, the latency signal may be stably generated with respect to a high frequency external clock.
However, when the latency signal is thus generated by being regularly latched using the 2-divided output clock signals, and the semiconductor memory device is typically set to operate in a low frequency mode, such as CAS latency 5, and the latency signal is generated with a 1 lock cycle loss. In other words, in case like CAS latency 5, a 1-divided output clock signal is more suitable to the generation of the latency signal than the 2-divided output clock signal. Accordingly, a latency circuit capable of selectively using a 1-division or 2-division output clock signal according to CAS latency is required.